IR drop reduction in CTS

Large cells can induce a large IR drop when they switch. In some designs, when power switches occur in regular vertical columns across the chip, it is advantageous to try and place large CTS cells, which may switch often, closer to the power switches to control the R part of the IR drop.

Cmd: create_ccopt_preferred_cell_stripe

(it’s a pity that I’m not working on multivoltage designs now, so… sad OTL.

EM reduction in CTS

EM could be taken into consideration during CTS in edi.

cmd: setCTSMode -useLefACLimit true

CTS tries to minimize EM violations during synthesis by resizing or inserting buffers to enhance the electrical current flow through the wires. If any wire exceeds the library values, CTS reports the violation in the  standard CTS report.

In order to perform EM analysis and optimization, LEF file must contain an AC Limit table. Period statement in the clock tree specification file is also needed (to cauculate Irms/Ipeak/Iavg).

So, what is AC Limit table in LEF file?

It specifies how much AC current a wire on this layer of a certain width can handle at a certain frequency in units of millamps per micron (mA/um).

Note: The true meaning of current density would have units of milliamps per square micron (mA/um2), however, the thickness of the metal layer is implicitly included, so the units in the table are milliamps per micron, where only the wire width varies.

keyword: ACCURRENTDENSITY or DCCURRENTDENSITY

example:

ACCURENTDENSITY AVERAGE

FREQUENCY 500 ;

WIDTH                0.040000  0.080000  0.099000 0.100000 …

TABLEENTRIES 1.011600  1.067800   1.078586   1.079040 …

What if there’s no AC limit table in tech lef files, what can we do to reduce EM in CTS with ck engine?

set “maxcap $value” in CTS specification file. CTS will avoid creating any clock net that exceeds the maxcap limit and therefore avoid any possible AC current limit violation.

 

EMreduction in ccopt

 

The EM avoidance function of ccopt lets you find a maximum total capacitance that a cell can drive without violating EM constraints and then set that capacitance value as the target maximum capacitance value for that cell.

Cmd: set_ccopt_property consider_em_constraints value

“value” could be one or more of rms/peark/avg

 

Note: the EM avoidance function is designed to avoid most of the EM violations on clock tree nets but not to eliminate all of them entirely. Because it computes the targets based on the preferred routing layers in routing information, generally, there are some violations left on the wires below the preferred layers. However, these too can be eliminated by using the Nanoroute EM rules.

 

Questions:

  1. when talking about EM in CTS, which one is taken into consideration? rms, average or peak?  by default, it checks Irms limit violations.
  2.  does power stripe has side effects on signal EM?
  3. 3 kinds of AC EM and DC EM?

 

 

zero-spacing routing guide on dpt layers

To create zero-spacing routing guide/blockage around terminals and boundaries on dpt layers to prevent multi-patterning violations:

ICC cmd:  create_mask_constraint_route_guides

EDI cmd: setNanoRouteMode -droutePostRouteSpreadWire

manual of EDI cmd:  post route wire spreading automatically avoids fractional spreading for DPT designs. If -droutePostRouteSpreadWire is enabled in 20nm designs and below, only 1 and 2 track wire spreading is done on dpt layers.

My question: if -droutePostRouteSpreadWire is disabled in 20nm designs and below, does wire spreading still work on dpt layers? if yes, 1 or 2 track spreading? how to check the information?