To create zero-spacing routing guide/blockage around terminals and boundaries on dpt layers to prevent multi-patterning violations:
ICC cmd: create_mask_constraint_route_guides
EDI cmd: setNanoRouteMode -droutePostRouteSpreadWire
manual of EDI cmd: post route wire spreading automatically avoids fractional spreading for DPT designs. If -droutePostRouteSpreadWire is enabled in 20nm designs and below, only 1 and 2 track wire spreading is done on dpt layers.
My question: if -droutePostRouteSpreadWire is disabled in 20nm designs and below, does wire spreading still work on dpt layers? if yes, 1 or 2 track spreading? how to check the information?